Recently, semiconductor devices such as a LSI or the like have been required to have higher density in order to meet requirements for reducing the mounting space or for improving the processing rate. As an example of a technology that achieves the high density, there has been known a multilayer wiring technology of manufacturing a multilayer substrate, such as a three-dimensional LSI or the like, by stacking multiple wiring substrates.
According to the multilayer wiring technology, a through-via-hole, which penetrates the wiring substrate and in which a conductive material such as copper (Cu) is buried, is typically formed in the wiring substrate in order to obtain electrical connection between the wiring substrates. As an example of a technology for forming the through-via-hole in which a conductive material is buried, there has been known an electroless plating method.
As a specific method of producing a wiring substrate, there is known a method in which a substrate having a recess is prepared, a barrier film is formed as a Cu diffusion barrier film within the recess of the substrate, and a seed film is formed on the barrier film by electroless Cu plating. Thereafter, Cu is buried in the recess by electrolytic Cu plating, and the substrate in which the Cu is buried is then thinned by a polishing method such as chemical mechanical polishing. Through this process, a wiring substrate having a through-via-hole in which the Cu is buried is manufactured.
To form the barrier film of the aforementioned wiring substrate, by adsorbing a catalyst onto the substrate in advance, a catalyst layer is formed. Further, by performing a plating process on the catalyst layer, a barrier film formed of Co—W—B layers is obtained. The barrier film is then baked, so that moisture within the barrier film is removed and the bond between metals is strengthened.
Meanwhile, when adsorbing the catalyst onto the substrate, a catalyst solution containing the catalyst is supplied onto the substrate having the recess, and then the catalyst is adsorbed onto a surface of the substrate and into the recess of the substrate. As a result, the catalyst layer is formed. If, however, the catalyst is adsorbed onto the surface of the substrate and into the recess of the substrate by supplying the catalyst solution onto the substrate, adhesivity of the catalyst adsorbed on the surface of the substrate may be insufficient, so that a plating layer formed by a subsequent plating process may be peeled off. Furthermore, if the catalyst solution remains within the recess of the substrate, the residues of the catalyst solution may have adverse effect upon the characteristic of the entire structure of the wiring substrate.
Patent Document 1: Japanese Patent Laid-open Publication No. 2013-067856